View X9221A_2878028.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev 1.1.2 7/16/02 characteristics subject to change without notice. 1 of 15 www.xicor.com X9221A dual digitally controlled potentiometer (xdcp ) features two xdcps in one package 2-wire serial interface register oriented format, 8 registers total directly write wiper position read wiper position store as many as four positions per pot instruction format quick transfer of register contents to resistor array direct write cell endurance?00,000 writes per bit per register resistor array values ?k ? , 10k ? , 50k ? resolution: 64 taps each pot 20-lead plastic dip and 20-lead soic packages description the X9221A integrates two digitally controlled potenti- ometers (xdcp) on a monolithic cmos integrated microcircuit. the digitally controlled potentiometer is implemented using 63 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the 2-wire bus interface. each potentiometer has associated with it a volatile wiper counter register (wcr) and 2 non- volatile data registers (dr0:dr1) that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array through the switches. power up recalls the con- tents of dr0 to the wcr. the xdcp can be used as a three-terminal potentiom- eter or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. 64 taps, 2-wire serial bus block diagram r1 r0 r3 r2 v h0 /r h0 v l0 /r l0 v w0 /r w0 wiper counter register (wcr) register array pot 1 wiper counter register (wcr) r1 r0 r3 r2 8 data scl sda a0 a1 a2 a3 interface and control circuitry v cc v ss pot 0 v h1 /r h1 v l1 /r l1 v w1 /r w1 a pplication n ote a v a i l a b l e an20 ?an42?3 ?an71 ?an73 ?an88 ?an91?2 ?an99 ?an115 ?an120 ?an124 ?an133 ?an134
X9221A characteristics subject to change without notice. 2 of 15 rev 1.1.2 7/16/02 www.xicor.com pin descriptions host interface pins serial clock (scl) the scl input is used to clock data into and out of the X9221A. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical val- ues, refer to the guidelines for calculating typical val- ues on the bus pull-up resistors graph. address the address inputs are used to set the least signi? cant 4 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9221A potentiometer pins v h /r h (v h0 /r h0 ? h1 /r h1 ), v l /r l (v l0 /r l0 ? l1 /r l1 ) the v h /r h and v l /r l inputs are equivalent to the ter- minal connections on either end of a mechanical potentiometer. v w /r w (v w0 /r w0 ? w1 /r w1 ) the wiper outputs are equivalent to the wiper output of a mechanical potentiometer. pin configuration pin names principles of operation the X9221A is a highly integrated microcircuit incor- porating two resistor arrays, their associated registers and counters and the serial interface logic providing direct communication between the host and the xdcp potentiometers. serial interface the X9221A supports a bidirectional bus oriented pro- tocol. the protocol de?es any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers and pro- vide the clock for both transmit and receive operations. therefore, the X9221A will be considered a slave device in all applications. clock and data conventions data states on the sda line can change only during scl low periods (t low ). sda state changes during scl high are reserved for indicating start and stop conditions. start condition all commands to the X9221A are preceded by the start condition, which is a high to low transition of sda while scl is high (t high ). the X9221A continu- ously monitors the sda and scl lines for the start condition, and will not respond to any command until this condition is met. stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda while scl is high. v w0 /r w0 v l0 /r l0 v h0 /r l0 a0 a2 v w1 /r w1 v l1 /r l1 v h1 /r h1 sda v ss 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v cc res res res a1 a3 scl res res res dip/soic X9221A symbol description scl serial clock sda serial data a0?3 address v h0 /r h0 ? h1 /r h1 , v l0 /r h0 ? l1 /r l0 potentiometers (terminal equivalent) v w0 /r w0 ? w1 /r w1 potentiometers (wiper equivalent) res reserved (do not connect)
X9221A characteristics subject to change without notice. 3 of 15 rev 1.1.2 7/16/02 www.xicor.com acknowledge acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. the transmitting device, either the master or the slave, will release the sda bus after transmitting eight bits. the master generates a ninth clock cycle and dur- ing this period the receiver pulls the sda line low to acknowledge that it successfully received the eight bits of data. see figure 7. the X9221A will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the com- mand byte. if the command is followed by a data byte the X9221A will respond with a ?al acknowledge. array description the X9221A is comprised of two resistor arrays. each array contains 63 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the ?ed terminals of a mechanical potentiometer (v h /r h and v l /r l inputs). at both ends of each array and between each resistor segment is a fet switch connected to the wiper (v w / r w ) output. within each individual array only one switch may be turned on at a time. these switches are controlled by the wiper counter register (wcr). the six least signi?ant bits of the wcr are decoded to select, and enable, one of sixty-four switches. the wcr may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the wcr. these data registers and the wcr can be read and written by the host system. device addressing following a start condition the master must output the address of the slave it is accessing. the most signi? cant four bits of the slave address are the device type identi?r (refer to figure 1 below). for the X9221A this is ?ed as 0101[b]. figure 1. slave address the next four bits of the slave address are the device address. the physical device address is de?ed by the state of the a0-a3 inputs. the X9221A compares the serial data stream with the address input state; a suc- cessful compare of all four address bits is required for the X9221A to respond with an acknowledge. acknowledge polling the disabling of the inputs, during the internal nonvola- tile write operation, can be used to take advantage of the typical 5ms eeprom write cycle time. once the stop condition is issued to indicate the end of the non- volatile write command the X9221A initiates the inter- nal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the device slave address. if the X9221A is still busy with the write operation no ack will be returned. if the X9221A has completed the write opera- tion an ack will be returned and the master can then proceed with the next operation. flow 1. ack polling sequence 1 0 0 a3 a2 a1 a0 device type identifier device address 1 nonvolatile write command completed enter ack polling issue start issue slave address ack returned? further operation? issue instruction proceed issue stop no yes yes proceed issue stop no
X9221A characteristics subject to change without notice. 4 of 15 rev 1.1.2 7/16/02 www.xicor.com instruction structure the next byte sent to the X9221A contains the instruc- tion and register pointer information. the four most signi?ant bits are the instruction. the next four bits point to one of two pots and when applicable they point to one of four associated registers. the format is shown below in figure 2. figure 2. instruction byte format t the four high order bits de?e the instruction. the sixth bit (p0) selects which one of the two potentiome- ters is to be affected by the instruction. the last two bits (r1 and r0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. four of the nine instructions end with the transmission of the instruction byte. the basic sequence is illus- trated in figure 3. these two-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a static ram. the response of the wiper to this action will be delayed t stpwv . a trans- fer from wcrs current wiper position to a data regis- ter is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between either potentiometer and their associated registers or it may occur between both of the potenti- ometers and one of their associated registers. four instructions require a three-byte sequence to complete. these instructions transfer data between the host and the X9221A; either between the host and one of the data registers or directly between the host and the wcr. these instructions are: read wcr, read the current wiper position of the selected pot; write wcr, change current wiper position of the selected pot; read data register, read the contents of the selected nonvolatile register; write data register, write a new value to the selected data register. the sequence of operations is shown in figure 4. the increment/decrement command is different from the other commands. once the command is issued and the X9221A has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a ?e tuning capability to the host. for each scl clock pulse (t high ) while sda is high, the selected wiper will move one resistor segment towards the v h /r h termi- nal. similarly, for each scl clock pulse while sda is low, the selected wiper will move one resistor seg- ment towards the v l /r l terminal. a detailed illustration of the sequence and timing for this operation are shown in figures 5 and 6 respectively. i1 i2 i3 i0 0 p0 r1 r0 potentiometer select register select instructions figure 3. two-byte command sequence s t a r t 0101a3a2a1a0 a i3 i2 i1 i0 0 p0 r1 r0 scl sda s t o p c k a c k
X9221A characteristics subject to change without notice. 5 of 15 rev 1.1.2 7/16/02 www.xicor.com figure 4. three-byte command sequence figure 5. increment/decrement command sequined e figure 6. increment/decrement timing limits s t a r t 0 1 0 1 a3 a2 a1 a0 a i3 i2 i1 i0 0 p0 r1 r0 scl sda s t o p 0 0 d5 d4 d3 d2 d1 d0 c k a c k a c k s t a r t 0 1 0 1 a3 a2 a1 a0 i3 i2 i1 i0 0 p0 r1 r0 scl sda s t o p x x i n c 1 i n c 2 i n c n d e c 1 d e c n a c k a c k scl sda v w /r w inc/dec cmd issued voltage out t clwv
X9221A characteristics subject to change without notice. 6 of 15 rev 1.1.2 7/16/02 www.xicor.com table 1. instruction set note: (7) n/a = not applicable or don? care; that is, a data register is not involved in the operation and need not be addressed (typ ical) figure 7. acknowledge response from receiver instruction instruction format operation i 3 i 2 i 1 i 0 0p 0 r 1 r 0 read wcr 1001 0 1/0n/a (7) n/a read the contents of the wiper counter register pointed to by p 0 write wcr 1010 0 1/0n/an/aw rite new value to the wiper counter register pointed to by p 0 read data register 1011 0 1/01/01/0 read the contents of the register pointed to by p 0 and r 1 ? 0 write data register 1100 0 1/01/01/0 write new value to the register pointed to by p 0 and r 1 ? 0 xfr data register to wcr 1101 0 1/01/01/0 transfer the contents of the register pointed to by p 0 and r 1 ? 0 to its associated wcr xfr wcr to data register 1110 0 1/01/01/0 transfer the contents of the wcr pointed to by p 0 to the register pointed to by r 1 ? 0 global xfr data register to wcr 0001n/an/a1/01/0 transfer the contents of the data registers pointed to by r 1 ? 0 of both pots to their respective wcr global xfr wcr to data register 1000n/an/a1/01/0 transfer the contents of all wcrs to their respective data registers pointed to by r 1 ? 0 of both pots increment/ decrement wiper 0010 0 1/0n/an/a enable increment/decrement of the wcr pointed to by p 0 scl from data output 1 89 start acknowledge master from transmitter data output from receiver
X9221A characteristics subject to change without notice. 7 of 15 rev 1.1.2 7/16/02 www.xicor.com detailed operation both xdcp potentiometers share the serial interface and share a common architecture. each potentiometer is comprised of a resistor array, a wiper counter regis- ter and four data registers. a detailed discussion of the register organization and array operation follows. wiper counter register the X9221A contains two wiper counter registers (wcr), one for each xdcp potentiometer. the wcr can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty- four switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via the write wcr instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the xfr data register instruction (parallel load); it can be modi?d one step at a time by the increment/ decrement instruction; ?ally, it is loaded with the con- tents of its data register zero (r0) upon power-up. the wcr is a volatile register; that is, its contents are lost when the X9221A is powered-down. although the register is automatically loaded with the value in r0 upon power-up, it should be noted this may be different from the value present at power-down. data registers each potentiometer has four nonvolatile data registers. these can be read or written directly by the host and data can be transferred between any of the four data registers and the wcr. it should be noted all opera- tions changing data in one of these registers is a non- volatile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. figure 8. detailed potentiometer block diagram serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input wiper counter register inc/dec logic up/dn clk modified scl up/dn v h /r h if wcr = 00[h] then v w /r w = v l /r l if wcr = 3f[h] then v w /r w = v h /r h 8 6 c d e o u n t e r e c o d v l /r l v w /r w
X9221A characteristics subject to change without notice. 8 of 15 rev 1.1.2 7/16/02 www.xicor.com absolute maximum ratings temperature under bias ....................?5? to +135? storage temperature .........................?5? to +150? voltage on sck, scl or any address input with respect to v ss ......................... ?v to +7v voltage on any v h /r h , v w /r w or v l /r l referenced to v ss ................................... +6v / ?.3v ? v = |v h /r h ? l /r l |........................................... 10.3v lead temperature (soldering, 10 seconds).........300? i w (10 seconds) ................................................. ?ma comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this speci?a- tion) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0? +70? industrial ?0? +85? supply voltage limits X9221A 5v ?0% analog characteristics (over recommended operating conditions unless otherwise stated.) symbol parameter limits test conditions min. typ. max. unit r total end to end resistance ?0 +20 % power rating 50 mw 25?, each pot i w wiper current ? +1 ma r w wiper resistance 40 130 ? wiper current = ?1ma v term voltage on any v h /r h , v w /r w or v l /r l pin ?.0 +5 v noise 120 dbv ref: 1v resolution 1.6 % see note 5 absolute linearity (1) ? +1 mi (3) v w(n)(actual) ? w(n)(expected) relative linearity (2) ?.2 +0.2 mi (3) v w(n + 1) ?v w(n) + mi ] temperature coefficient ?00 ppm/? see note 5 radiometric temperature coefficient ?0 ppm/? see note 5 c h /c l /c w potentiometer capacitances 10/10/25 pf see circuit #3
X9221A characteristics subject to change without notice. 9 of 15 rev 1.1.2 7/16/02 www.xicor.com d.c. operating characteristics (over recommended operating conditions unless otherwise stated.) notes: (1) absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position whe n used as a potentiometer. (2) relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a poten- tiometer. it is a measure of the error in step size. (3) mi = rtot/63 or (v h /r h ? l /r l )/63, single pot endurance and data retention capacitance power-up timing notes: (5) this parameter is periodically sampled and not 100% tested. (6) t pur and t puw are the delays required from the time v cc is stable until the speci?d operation can be initiated. these parameters are periodically sampled and not 100% tested. power up requirements (power up sequencing can affect correct recall of the wiper registers) the preferred power-on sequence is as follows: first v cc , then the potentiometer pins. it is suggested that v cc reach 90% of its ?al value before power is applied to the potentiometer pins. the v cc ramp rate speci?ation should be met, and any glitches or slope changes in the v cc line should be held to <100mv if possible. also, v cc should not reverse polarity by more than 0.5v. symbol parameter limits test conditions min. typ. max. unit l cc supply current (active) 3 ma f scl = 100khz, sda = open, other inputs = v ss i sb v cc current (standby) 200 500 ? scl = sda = v cc , addr. = v ss i li input leakage current 10 ? v in = v ss to v cc i lo output leakage current 10 ? v out = v ss to v cc v ih input high voltage 2 v cc + 1 v v il input low voltage ? 0.8 v v ol output low voltage 0.4 v i ol = 3ma parameter min. unit minimum endurance 100,000 data changes per bit per register data retention 100 years symbol parameter max. unit test conditions c i/o (5) input/output capacitance (sda) 8 pf v i/o = 0v c in (5) input capacitance (a0, a1, a2, a3 and scl) 6 pf v in = 0v symbol parameter min. max. unit t pur (6) power-up to initiation of read operation 1 ms t puw (6) power-up to initiation of write operation 5 ms t r v cc v cc power-up ramp rate 0.2 50 v/msec
X9221A characteristics subject to change without notice. 10 of 15 rev 1.1.2 7/16/02 www.xicor.com symbol table equivalent a.c. test circuit circuit #3 spice macro model guidelines for calculating typical values of bus pull-up resistors waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance 5v 1533 ? 100pf sda output r h c h 10pf c w r l c l r w r total 25pf 10pf macro model 120 100 80 40 60 20 20 40 60 80 100 120 0 0 bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =1.8k ? resistance (k ? ) a.c. conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5
X9221A characteristics subject to change without notice. 11 of 15 rev 1.1.2 7/16/02 www.xicor.com a.c. characteristics (over recommended operating conditions unless otherwise stated) symbol parameter limits unit reference figure min. max. f scl scl clock frequency 0 100 khz 10 t low clock low period 4700 ns 10 t high clock high period 4000 ns 10 t r scl and sda rise time 1000 ns 10 t f scl and sda fall time 300 ns 10 t i noise suppression time constant (glitch filter) 100 ns 10 t su:sta start condition setup time (for a repeated start condition) 4700 ns 10 & 12 t hd:sta start condition hold time 4000 ns 10 & 12 t su:dat data in setup time 250 ns 10 t hd:dat data in hold time 0 ns 10 t aa scl low to sda data out valid 300 3500 ns 11 t dh data out hold time 300 ns 11 t su:sto stop condition setup time 4700 ns 10 & 12 t buf bus free time prior to new transmission 4700 ns 10 t wr write cycle time (nonvolatile write operation) 10 ms 13 t stpwv wiper response time from stop generation 1000 ? 13 t clwv wiper response from scl low 500 ? 6
X9221A characteristics subject to change without notice. 12 of 15 rev 1.1.2 7/16/02 www.xicor.com timing diagrams figure 10. input bus timing figure 11. output bus timing figure 12. start stop timing figure 13. write cycle and wiper response timing t high t su:sta t hd:sta t hd:dat t su:dat t low t f t su:sto t r t buf scl sda (data in) t aa t dh scl sda sda out (ack) sda out sda out t su:sto scl sda (data in) t hd:sta t su:sta stop condition start condition scl sda wiper output clock 8 sda in clock 9 ack stop t wr t stpwv start
X9221A characteristics subject to change without notice. 13 of 15 rev 1.1.2 7/16/02 www.xicor.com packaging information 0.022 (0.559) 0.014 (0.356) (3.81) 0.150 (2.92) 0.1150 0.10 (bsc) (2.54) 1.060 (26.92) 0.980 (24.89) 0.900 (23.66) ref. pin 1 index 0.195 (4.95) 0.115 (2.92) 0.015 (0.38) pin 1 seating plane 0.070 (1.778) 0.045 (1.143) 0.280 (7.11) 0.240 (6.096) 0.005 (0.127) 0 15 20-lead plastic dual in-line package type p 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.014 (0.356) 0.008 (0.2032) 0.300 (7.62) (bsc) note:
X9221A characteristics subject to change without notice. 14 of 15 rev 1.1.2 7/16/02 www.xicor.com packaging information 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) pin 1 pin 1 index 0.050 (1.27) 0.496 (12.60) 0.508 (12.90) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4x) 7 20-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.420" 0.050" typical 0.050" typical 0.030" typical 20 places footprint 0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.007 (0.18) 0.011 (0.28) 08 x 45
X9221A characteristics subject to change without notice. 15 of 15 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2002 patents pending rev 1.1.2 7/16/02 www.xicor.com ordering information X9221A y p t v v cc limits blank = 5v ?0% temperature range blank = commercial = 0? to +70? i = industrial = ?0? to +85? package p = 20-lead plastic dip s = 20-lead soic potentiometer organization pot 0 pot 1 y = 2k 2k w = 10k 10k u = 50k 50k device

▲Up To Search▲

Price & Availability of X9221A

	To Download X9221A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .